1. Field of the Invention
The present invention relates to an image sensor and, more particularly, to a CMOS image sensor integrated with a pinned photodiode, which is capable of reducing clock feedthrough and improving dynamic range.
2. Description of the Prior Art
CMOS (complementary metal-oxide-semiconductor) image sensor or CMOS sensor is known in the art. Generally, a CMOS sensor includes a plurality of unit pixels having a light-sensing region and a peripheral circuit region. Each of the unit pixels also includes a light-sensing element such as a photodiode formed in the light-sensing region and a plurality of transistors formed on the peripheral circuit region. The photodiode senses incident light and accumulates image charges that are generated due to the incident light.
FIG. 1 illustrates a layout of four-transistor (4T) pixel cell 10 of a conventional CMOS sensor. FIG. 2 is a schematic, cross-sectional view of the CMOS sensor of FIG. 1 taken along line I-I′. The CMOS sensor pixel cell 10 includes a charge-accumulating region 20 in an underlying portion of the substrate. A pinned photodiode 22 is formed in the charge-accumulating region 20. A transfer gate 30 is provided for transferring photoelectric charges generated in the charge-accumulating region 20 to a floating diffusion region (sensing node) 25. The pinned photodiode is termed “pinned” because the potential in the photodiode is pinned to a constant value when the photodiode is fully depleted.
Typically, the floating diffusion region 25 is coupled to a gate 34 of a source follower transistor. The source follower transistor provides an output signal to a row select access transistor having a gate 36. A reset transistor having a gate 32 resets the floating diffusion region 25 to a specified charge level before each charge transfer from the charge-accumulating region 20. As best seen in FIG. 1, N-type doped source/drain regions 27 are provided on either side of the transistor gates 32, 34, 36. The floating diffusion region 25 adjacent the transfer gate 30 is also N-type.
As best seen in FIG. 2, the charge-accumulating region 20 is formed as a pinned photodiode 22, which has a PNP junction region consisting of a surface P+ pinning layer 24, an N-type photodiode region 26 and a P-type substrate 12. The pinned photodiode 22 includes two P-type regions 12, 24 so that the N-type photodiode region 26 is fully depleted at a pinning voltage. Trench isolation regions 15 are formed in the P-type substrate 12 adjacent the charge-accumulating region 20. The trench isolation regions 15 are typically formed using a conventional shallow trench isolation (STI) process or by using a local oxidation of silicon (LOCOS) process.
CMOS sensors typically suffer from narrow dynamic range and poor charge transfer efficiency. As shown in FIG. 2, the overlapping portion between the gate 30 and the underlying N-type photodiode region 26 is designated as “A”. It has been known that in order to increase the charge transfer efficiency of the CMOS sensor, “A” should be made as large as possible. The distance between the surface P+ pinning layer 24 and the P type substrate 12 underneath the gate 30 is designated as “B”. If the distance “B” is too small, pinch-off occurs resulting in narrow dynamic range and undesirable image lags.
A conventional non-self alignment method for forming the pixel sensor can provide larger overlapping portion “A” and distance “B”. According to the conventional non-self-alignment method, the N type photodiode region 26 is implanted into the pre-selected areas of the P-type substrate 12 using a photomask prior to the definition of the transfer gate 30. However, the prior art non-self-aligned method suffers from so-called fixed pattern noise due to misalignment of the lithography and non-uniformity of the overlapping portion “A” among pixels.
Referring to FIG. 3, a schematic potential diagram of a CMOS sensor during operation is demonstrated. On the other hand, the above-described prior art CMOS sensor has another drawback in that a potential “pocket” indicated by numeral number 50 forms due to an excessively large overlapping portion “A”. The potential “pocket” 50 is caused by a large number of trapped electrons accumulated underneath the gate 30, which leads to deteriorated clock feed-through of the gate 30 of the transfer transistor, image lag, and also poor dynamic range.